Vending Machine FSM Project (ECE 271)
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This FPGA vending machine project was designed using SystemVerilog, Quartus, and the DE10-Lite development board. The system accepted nickels, dimes, and quarters, displayed balance on dual 7-segment displays, and vended automatically at 50¢ while supporting change return and refund logic using the largest coin denominations available. The design used a modular architecture with separate FSM, clock divider, and display decoder modules, along with edge detection to prevent double-counting and unstable inputs. The project was validated through ModelSim simulation and physical FPGA testing.
Figure 1. FSM diagram showing balance states and coin-triggered vending logic.
Figure 2. DE10-Lite FPGA hardware implementation during system testing.
Key Features:
• Accepted nickels, dimes, and quarters
• Vended automatically at 50¢ or greater
• Supported refund and automatic change return
• Displayed live balance on dual 7-segment displays
• Used modular SystemVerilog architecture
• Implemented edge detection for reliable inputs
• Verified through simulation and FPGA testing
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